For successive approximation (SAR) AD converters, a technique for improving resolution per cycle in order to increase sample frequency has been proposed (first conventional technique).
Furthermore, for a residual signal generating section of the successive approximation AD converter which is required for comparison, a technique using a 4-input amplifier has been proposed (second conventional technique).
Additionally, a technique for reducing the number of capacitive DACs in the successive approximation AD converter has been proposed (third conventional technique).
A circuit according to the first conventional technique mainly includes a plurality of (three) comparators, a plurality of (three) capacitive DACs, and a control circuit. More analog voltage comparison points need to be provided as the resolution is improved. Thus, a circuit of a type that converts a resolution of at least 2 bits at a time includes a plurality of comparators. An essential point of this circuit is that a plurality of capacitive DACs are used to generate a plurality of residual signals. The plurality of residual signals are connected to the respective comparators. Each of the comparators compares a residual signal with a ground voltage to determine the difference between the signals. The control circuit reflects the result of the comparison in the plurality of capacitive DACs, and repeats a successive approximation AD conversion a required number of times. The above-described circuit configuration improves the resolution per cycle. However, the configuration requires the same number of capacitive DACs as that of the comparators, disadvantageously increasing the area of the circuit.
A circuit according to the third conventional technique includes a plurality of (at least two) capacitances, a plurality of comparators, a resistive DAC, and a control circuit. An essential point of this circuit is that the number of capacitances is reduced by application of an interpolation technique.
In the interpolation, two source residual signals are provided and a plurality of residual signals are generated between the two residual signals. The technique allows the two capacitive DACs to generate residual signals that are supplied to the plurality of comparators. This enables a reduction in circuit area compared to the first conventional technique. In actuality, the third conventional technique simplifies the circuit configuration of the capacitances by separating the configuration of the capacitive DACs into the capacitances and the resistive DAC. However, even the interpolation requires at least two capacitances (or capacitive DACs), leading to the need for a reduction in the number of capacitive DACs. Furthermore, in actuality, the linear range of signals that can be handled within the circuit is not infinite, and it is thus difficult to achieve interpolation with a high resolution using the two capacitive DACs. Thus, the circuit according to the third conventional technique also has a challenge to reduce the area of the capacitive DACs (or capacitances).
A circuit according to the second conventional technique mainly includes a plurality of amplifiers (four inputs and one output), a plurality of comparators (encoders), and a residual amplifier. This circuit allows the 4 input 1 output amplifier to generate residual signals for the comparators. Reference voltages used for a residual calculation are generated by a resistive DAC. Unlike the circuit according to the first conventional technique, the circuit according to the second conventional, technique fails to include a circuit (sampler) that stores an input signal. Thus, the circuit cannot be applied to such a successive approximation AD converter as repeatedly uses the circuit to obtain a high resolution and a pipelined AD converter in which an AD converting operation and a residual signal amplifying operation do not temporally overlap. The circuit needs to increase the resolution of the resistive DAC and the numbers of amplifiers and comparators using power-of-two scaling, according to the resolution of the AD converter (flash AD converter). This disadvantageously increases the circuit area when a high-resolution AD converter is configured.